// Copyright (C) 1953-2022 NUDT
// Verilog module name - management_interface_hub
// Version: V3.4.0.20220225
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         command interface transfer
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module management_interface_hub
    (
        i_clk,
        i_rst_n,

        iv_command,   
        i_command_wr,           
        
        ov_addr,
        ov_wdata,  

        o_wr_ffi_p8,
        o_rd_ffi_p8,
        o_wr_dex_p8,
        o_rd_dex_p8,
        o_wr_ctx_p8,
        o_rd_ctx_p8,
                   
        o_wr_ffi_p0,
        o_rd_ffi_p0,
        o_wr_dex_p0,
        o_rd_dex_p0,
        o_wr_ctx_p0,
        o_rd_ctx_p0,
                  
        o_wr_ffi_p1,
        o_rd_ffi_p1,
        o_wr_dex_p1,
        o_rd_dex_p1,
        o_wr_ctx_p1,
        o_rd_ctx_p1,
                   
        o_wr_ffi_p2,
        o_rd_ffi_p2,
        o_wr_dex_p2,
        o_rd_dex_p2,
        o_wr_ctx_p2,
        o_rd_ctx_p2,
                  
        o_wr_ffi_p3,
        o_rd_ffi_p3,
        o_wr_frm,
        o_rd_frm,
        o_wr_tic,
        o_rd_tic,                 

        o_wr_frl   ,      
        o_rd_frl   ,
        
        o_wr_pcb   ,
        o_rd_pcb   ,
        
        o_wr_qgc0  ,
        o_rd_qgc0  ,
                   
        o_wr_qgc1  ,
        o_rd_qgc1  ,
                   
        o_wr_qgc2  ,
        o_rd_qgc2  ,
                   
        o_wr_sim  ,
        o_rd_sim  ,

        o_wr_rfe      , 
        o_rd_rfe      ,
        
        o_wr_mac_p0   ,
        o_rd_mac_p0   ,
        
        o_wr_mac_p1   ,
        o_rd_mac_p1   ,
        
        o_wr_mac_p2   ,
        o_rd_mac_p2   ,
        
        o_wr_mac_p3   ,
        o_rd_mac_p3   ,
        
        o_wr_tau   ,
        o_rd_tau   ,        
        
        i_wr_ffi_p8,
        iv_addr_ffi_p8,
        iv_rdata_ffi_p8,

        i_wr_dex_p8,
        iv_addr_dex_p8,
        iv_rdata_dex_p8,

        i_wr_ctx_p8,
        iv_addr_ctx_p8,
        iv_rdata_ctx_p8,

        i_wr_ffi_p0,
        iv_addr_ffi_p0,
        iv_rdata_ffi_p0,

        i_wr_dex_p0,
        iv_addr_dex_p0,
        iv_rdata_dex_p0,

        i_wr_ctx_p0,
        iv_addr_ctx_p0,
        iv_rdata_ctx_p0,

        i_wr_ffi_p1,
        iv_addr_ffi_p1,
        iv_rdata_ffi_p1,

        i_wr_dex_p1,
        iv_addr_dex_p1,
        iv_rdata_dex_p1,

        i_wr_ctx_p1,
        iv_addr_ctx_p1,
        iv_rdata_ctx_p1,

        i_wr_ffi_p2,
        iv_addr_ffi_p2,
        iv_rdata_ffi_p2,

        i_wr_dex_p2,
        iv_addr_dex_p2,
        iv_rdata_dex_p2,

        i_wr_ctx_p2,
        iv_addr_ctx_p2,
        iv_rdata_ctx_p2,

        i_wr_ffi_p3,
        iv_addr_ffi_p3,
        iv_rdata_ffi_p3,

        i_wr_frm        ,
        iv_addr_frm     ,       
        iv_rdata_frm    ,       
                        
        i_wr_tic        ,       
        iv_addr_tic     ,       
        iv_rdata_tic    ,       

        i_wr_pcb,
        iv_addr_pcb,
        iv_rdata_pcb,
        
        i_wr_frl,
        iv_addr_frl,
        iv_rdata_frl,        

        i_wr_qgc0,
        iv_addr_qgc0,
        iv_rdata_qgc0,

        i_wr_qgc1,
        iv_addr_qgc1,
        iv_rdata_qgc1,

        i_wr_qgc2,
        iv_addr_qgc2,
        iv_rdata_qgc2,

        i_wr_sim        ,
        iv_addr_sim     ,
        iv_rdata_sim    ,
        
        i_wr_rfe        ,
        iv_addr_rfe     ,
        iv_rdata_rfe    ,
        
        i_wr_mac_p0     ,
        iv_addr_mac_p0  ,
        iv_rdata_mac_p0 ,
        
        i_wr_mac_p1     ,
        iv_addr_mac_p1  ,
        iv_rdata_mac_p1 ,
        
        i_wr_mac_p2     ,
        iv_addr_mac_p2  ,
        iv_rdata_mac_p2 ,
        
        i_wr_mac_p3     ,
        iv_addr_mac_p3  ,
        iv_rdata_mac_p3 ,
        
        i_wr_tau        ,
        iv_addr_tau     ,
        iv_rdata_tau    ,
        
        o_command_ack_wr,
        ov_command_ack  ,

        ov_tse_ver                         ,
        ov_hpriority_be_police_threshold   ,
        ov_rc_threshold_value              ,
        ov_lpriority_be_police_threshold   ,
        o_qbv_or_qch                       ,
        ov_time_slot_length                ,
        ov_schedule_period              
    );
// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n; 
//receive command           
input       [63:0]      iv_command;   
input                   i_command_wr;           
  
output      [18:0]      ov_addr;
output      [31:0]      ov_wdata;
//to p8                 
output                  o_wr_ffi_p8;
output                  o_rd_ffi_p8;
output                  o_wr_dex_p8;
output                  o_rd_dex_p8;
output                  o_wr_ctx_p8;
output                  o_rd_ctx_p8;
//to p0                 
output                  o_wr_ffi_p0;
output                  o_rd_ffi_p0;
output                  o_wr_dex_p0;
output                  o_rd_dex_p0;
output                  o_wr_ctx_p0;
output                  o_rd_ctx_p0;
//to p1                 
output                  o_wr_ffi_p1;
output                  o_rd_ffi_p1;
output                  o_wr_dex_p1;
output                  o_rd_dex_p1;
output                  o_wr_ctx_p1;
output                  o_rd_ctx_p1;
//to p2                 
output                  o_wr_ffi_p2;
output                  o_rd_ffi_p2;
output                  o_wr_dex_p2;
output                  o_rd_dex_p2;
output                  o_wr_ctx_p2;
output                  o_rd_ctx_p2;
//to p3                 
output                  o_wr_ffi_p3;
output                  o_rd_ffi_p3;
output                  o_wr_frm;
output                  o_rd_frm;
output                  o_wr_tic;
output                  o_rd_tic;        									
//to pcb                
output                  o_wr_pcb;
output                  o_rd_pcb;
//to frl
output                  o_wr_frl;
output                  o_rd_frl;
//to qgc                
output                  o_wr_qgc0;
output                  o_rd_qgc0;
                        
output                  o_wr_qgc1;
output                  o_rd_qgc1;
                        
output                  o_wr_qgc2;
output                  o_rd_qgc2;
                        
output                  o_wr_sim;
output                  o_rd_sim; 

output                  o_wr_rfe     ; 
output                  o_rd_rfe     ;

output                  o_wr_mac_p0  ;
output                  o_rd_mac_p0  ;

output                  o_wr_mac_p1  ; 
output                  o_rd_mac_p1  ;

output                  o_wr_mac_p2  ;
output                  o_rd_mac_p2  ;

output                  o_wr_mac_p3  ;
output                  o_rd_mac_p3  ; 

output                  o_wr_tau     ;
output                  o_rd_tau     ;         
//from ffi_p8 
input                   i_wr_ffi_p8;
input        [18:0]     iv_addr_ffi_p8;
input        [31:0]     iv_rdata_ffi_p8;
//from dex_p8 
input                   i_wr_dex_p8;
input        [18:0]     iv_addr_dex_p8;
input        [31:0]     iv_rdata_dex_p8;
//from ctx_p8 
input                   i_wr_ctx_p8;
input        [18:0]     iv_addr_ctx_p8;
input        [31:0]     iv_rdata_ctx_p8;
//from ffi_p0 
input                   i_wr_ffi_p0;
input        [18:0]     iv_addr_ffi_p0;
input        [31:0]     iv_rdata_ffi_p0;
//from dex_p0 
input                   i_wr_dex_p0;
input        [18:0]     iv_addr_dex_p0;
input        [31:0]     iv_rdata_dex_p0;
//from ctx_p0 
input                   i_wr_ctx_p0;
input        [18:0]     iv_addr_ctx_p0;
input        [31:0]     iv_rdata_ctx_p0;
//from ffi_p1 
input                   i_wr_ffi_p1;
input        [18:0]     iv_addr_ffi_p1;
input        [31:0]     iv_rdata_ffi_p1;
//from dex_p1 
input                   i_wr_dex_p1;
input        [18:0]     iv_addr_dex_p1;
input        [31:0]     iv_rdata_dex_p1;
//from ctx_p1 
input                   i_wr_ctx_p1;
input        [18:0]     iv_addr_ctx_p1;
input        [31:0]     iv_rdata_ctx_p1;
//from ffi_p2 
input                   i_wr_ffi_p2;
input        [18:0]     iv_addr_ffi_p2;
input        [31:0]     iv_rdata_ffi_p2;
//from dex_p2 
input                   i_wr_dex_p2;
input        [18:0]     iv_addr_dex_p2;
input        [31:0]     iv_rdata_dex_p2;
//from ctx_p2 
input                   i_wr_ctx_p2;
input        [18:0]     iv_addr_ctx_p2;
input        [31:0]     iv_rdata_ctx_p2;
//from ffi_p3 
input                   i_wr_ffi_p3;
input        [18:0]     iv_addr_ffi_p3;
input        [31:0]     iv_rdata_ffi_p3;
//from dex_p3 
input                   i_wr_frm        ;
input        [18:0]     iv_addr_frm     ;
input        [31:0]     iv_rdata_frm    ;
//from ctx_p3           
input                   i_wr_tic        ;
input        [18:0]     iv_addr_tic     ;
input        [31:0]     iv_rdata_tic    ;
//from pcb 
input                   i_wr_pcb;
input        [18:0]     iv_addr_pcb;
input        [31:0]     iv_rdata_pcb;
//from frl 
input                   i_wr_frl          ;
input        [18:0]     iv_addr_frl       ;
input        [31:0]     iv_rdata_frl      ;
//from qgc 
input                   i_wr_qgc0;
input        [18:0]     iv_addr_qgc0;
input        [31:0]     iv_rdata_qgc0;

input                   i_wr_qgc1;
input        [18:0]     iv_addr_qgc1;
input        [31:0]     iv_rdata_qgc1;

input                   i_wr_qgc2;
input        [18:0]     iv_addr_qgc2;
input        [31:0]     iv_rdata_qgc2;

input                   i_wr_sim        ;
input        [18:0]     iv_addr_sim     ;
input        [31:0]     iv_rdata_sim    ;

input                   i_wr_rfe        ;
input        [18:0]     iv_addr_rfe     ;
input        [31:0]     iv_rdata_rfe    ;

input                   i_wr_mac_p0     ;
input        [18:0]     iv_addr_mac_p0  ;
input        [31:0]     iv_rdata_mac_p0 ;

input                   i_wr_mac_p1     ;
input        [18:0]     iv_addr_mac_p1  ;
input        [31:0]     iv_rdata_mac_p1 ;

input                   i_wr_mac_p2     ;
input        [18:0]     iv_addr_mac_p2  ;
input        [31:0]     iv_rdata_mac_p2 ;

input                   i_wr_mac_p3     ;
input        [18:0]     iv_addr_mac_p3  ;
input        [31:0]     iv_rdata_mac_p3 ;

input                   i_wr_tau     ;
input        [18:0]     iv_addr_tau  ;
input        [31:0]     iv_rdata_tau ;

output                  o_command_ack_wr;
output       [63:0]     ov_command_ack; 

output       [31:0]     ov_tse_ver                        ;
output       [8:0]      ov_hpriority_be_police_threshold           ;
output       [8:0]      ov_rc_threshold_value             ;
output       [8:0]      ov_lpriority_be_police_threshold  ;         
output                  o_qbv_or_qch                      ;
output       [10:0]     ov_time_slot_length               ;
output       [10:0]     ov_schedule_period                ;
//to grm                
wire                    w_wr_cpa2grm;
wire                    w_rd_cpa2grm;
wire                    w_wr_grm2cag     ;
wire         [18:0]     wv_addr_grm2cag  ;
wire         [31:0]     wv_rdata_grm2cag ;	
tse_command_parse tse_command_parse_inst(
.i_clk        (i_clk       ),
.i_rst_n      (i_rst_n     ),

.iv_command   (iv_command  ),   
.i_command_wr (i_command_wr),           

.ov_addr      (ov_addr     ),
.ov_wdata     (ov_wdata    ),

.o_wr_ffi_p8  (o_wr_ffi_p8  ),
.o_rd_ffi_p8  (o_rd_ffi_p8  ),
.o_wr_dex_p8  (o_wr_dex_p8  ),
.o_rd_dex_p8  (o_rd_dex_p8  ),

.o_wr_ffi_p0  (o_wr_ffi_p0  ),
.o_rd_ffi_p0  (o_rd_ffi_p0  ),
.o_wr_dex_p0  (o_wr_dex_p0  ),
.o_rd_dex_p0  (o_rd_dex_p0  ),

.o_wr_ffi_p1  (o_wr_ffi_p1  ),
.o_rd_ffi_p1  (o_rd_ffi_p1  ),
.o_wr_dex_p1  (o_wr_dex_p1  ),
.o_rd_dex_p1  (o_rd_dex_p1  ),

.o_wr_ffi_p2  (o_wr_ffi_p2  ),
.o_rd_ffi_p2  (o_rd_ffi_p2  ),
.o_wr_dex_p2  (o_wr_dex_p2  ),
.o_rd_dex_p2  (o_rd_dex_p2  ),

.o_wr_ffi_p3  (o_wr_ffi_p3  ),
.o_rd_ffi_p3  (o_rd_ffi_p3  ),
.o_wr_frm     (o_wr_frm ),
.o_rd_frm     (o_rd_frm ),
.o_wr_tic     (o_wr_tic ),
.o_rd_tic     (o_rd_tic ),

.o_wr_grm     (w_wr_cpa2grm     ),
.o_rd_grm     (w_rd_cpa2grm     ),

.o_wr_pcb     (o_wr_pcb     ),
.o_rd_pcb     (o_rd_pcb     ),

.o_wr_frl     (o_wr_frl     ),
.o_rd_frl     (o_rd_frl     ),

.o_wr_qgc0    (o_wr_qgc0    ),
.o_rd_qgc0    (o_rd_qgc0    ),

.o_wr_qgc1    (o_wr_qgc1    ),
.o_rd_qgc1    (o_rd_qgc1    ),

.o_wr_qgc2    (o_wr_qgc2    ),
.o_rd_qgc2    (o_rd_qgc2    ),

.o_wr_sim     (o_wr_sim    ),
.o_rd_sim     (o_rd_sim    ),

.o_wr_rfe     (o_wr_rfe   ),
.o_rd_rfe     (o_rd_rfe   ),  
               
.o_wr_mac_p0  (o_wr_mac_p0),
.o_rd_mac_p0  (o_rd_mac_p0),  
               
.o_wr_mac_p1  (o_wr_mac_p1),
.o_rd_mac_p1  (o_rd_mac_p1),  
               
.o_wr_mac_p2  (o_wr_mac_p2),
.o_rd_mac_p2  (o_rd_mac_p2),  
               
.o_wr_mac_p3  (o_wr_mac_p3),
.o_rd_mac_p3  (o_rd_mac_p3),

.o_wr_tau     (o_wr_tau),
.o_rd_tau     (o_rd_tau)
); 
tse_commandack_generate tse_commandack_generate_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),          

.o_command_ack_wr                           (o_command_ack_wr),
.ov_command_ack                             (ov_command_ack),

.i_wr_ffi_p8                                (i_wr_ffi_p8             ),
.iv_addr_ffi_p8                             (iv_addr_ffi_p8          ),
.iv_rdata_ffi_p8                            (iv_rdata_ffi_p8         ),

.i_wr_dex_p8                                (i_wr_dex_p8             ),
.iv_addr_dex_p8                             (iv_addr_dex_p8          ),
.iv_rdata_dex_p8                            (iv_rdata_dex_p8         ),

.i_wr_ctx_p8                                (i_wr_ctx_p8             ),
.iv_addr_ctx_p8                             (iv_addr_ctx_p8          ),
.iv_rdata_ctx_p8                            (iv_rdata_ctx_p8         ),

.i_wr_ffi_p0                                (i_wr_ffi_p0             ),
.iv_addr_ffi_p0                             (iv_addr_ffi_p0          ),
.iv_rdata_ffi_p0                            (iv_rdata_ffi_p0         ),

.i_wr_dex_p0                                (i_wr_dex_p0             ),
.iv_addr_dex_p0                             (iv_addr_dex_p0          ),
.iv_rdata_dex_p0                            (iv_rdata_dex_p0         ),

.i_wr_ctx_p0                                (i_wr_ctx_p0             ),
.iv_addr_ctx_p0                             (iv_addr_ctx_p0          ),
.iv_rdata_ctx_p0                            (iv_rdata_ctx_p0         ),

.i_wr_ffi_p1                                (i_wr_ffi_p1             ),
.iv_addr_ffi_p1                             (iv_addr_ffi_p1          ),
.iv_rdata_ffi_p1                            (iv_rdata_ffi_p1         ),

.i_wr_dex_p1                                (i_wr_dex_p1             ),
.iv_addr_dex_p1                             (iv_addr_dex_p1          ),
.iv_rdata_dex_p1                            (iv_rdata_dex_p1         ),

.i_wr_ctx_p1                                (i_wr_ctx_p1             ),
.iv_addr_ctx_p1                             (iv_addr_ctx_p1          ),
.iv_rdata_ctx_p1                            (iv_rdata_ctx_p1         ),

.i_wr_ffi_p2                                (i_wr_ffi_p2             ),
.iv_addr_ffi_p2                             (iv_addr_ffi_p2          ),
.iv_rdata_ffi_p2                            (iv_rdata_ffi_p2         ),

.i_wr_dex_p2                                (i_wr_dex_p2             ),
.iv_addr_dex_p2                             (iv_addr_dex_p2          ),
.iv_rdata_dex_p2                            (iv_rdata_dex_p2         ),

.i_wr_ctx_p2                                (i_wr_ctx_p2             ),
.iv_addr_ctx_p2                             (iv_addr_ctx_p2          ),
.iv_rdata_ctx_p2                            (iv_rdata_ctx_p2         ),

.i_wr_ffi_p3                                (i_wr_ffi_p3             ),
.iv_addr_ffi_p3                             (iv_addr_ffi_p3          ),
.iv_rdata_ffi_p3                            (iv_rdata_ffi_p3         ),

.i_wr_frm                                   (i_wr_frm            ),
.iv_addr_frm                                (iv_addr_frm         ),
.iv_rdata_frm                               (iv_rdata_frm        ),
                                             
.i_wr_tic                                   (i_wr_tic            ),
.iv_addr_tic                                (iv_addr_tic         ),
.iv_rdata_tic                               (iv_rdata_tic        ),

.i_wr_grm                                   (w_wr_grm2cag                ),
.iv_addr_grm                                (wv_addr_grm2cag             ),
.iv_rdata_grm                               (wv_rdata_grm2cag            ),

.i_wr_pcb                                   (i_wr_pcb                ),
.iv_addr_pcb                                (iv_addr_pcb             ),
.iv_rdata_pcb                               (iv_rdata_pcb            ),

.i_wr_frl                                   (i_wr_frl                ),
.iv_addr_frl                                (iv_addr_frl             ),
.iv_rdata_frl                               (iv_rdata_frl            ),

.i_wr_qgc0                                  (i_wr_qgc0               ),
.iv_addr_qgc0                               (iv_addr_qgc0            ),
.iv_rdata_qgc0                              (iv_rdata_qgc0           ),

.i_wr_qgc1                                  (i_wr_qgc1               ),
.iv_addr_qgc1                               (iv_addr_qgc1            ),
.iv_rdata_qgc1                              (iv_rdata_qgc1           ),

.i_wr_qgc2                                  (i_wr_qgc2               ),
.iv_addr_qgc2                               (iv_addr_qgc2            ),
.iv_rdata_qgc2                              (iv_rdata_qgc2           ),

.i_wr_sim                                   (i_wr_sim                ),
.iv_addr_sim                                (iv_addr_sim             ),
.iv_rdata_sim                               (iv_rdata_sim            ),

.i_wr_rfe                                   (i_wr_rfe                ),
.iv_addr_rfe                                (iv_addr_rfe             ),
.iv_rdata_rfe                               (iv_rdata_rfe            ),

.i_wr_mac_p0                                (i_wr_mac_p0                ),
.iv_addr_mac_p0                             (iv_addr_mac_p0             ),
.iv_rdata_mac_p0                            (iv_rdata_mac_p0            ),
                                            
.i_wr_mac_p1                                (i_wr_mac_p1                ),
.iv_addr_mac_p1                             (iv_addr_mac_p1             ),
.iv_rdata_mac_p1                            (iv_rdata_mac_p1            ),
                                            
.i_wr_mac_p2                                (i_wr_mac_p2                ),
.iv_addr_mac_p2                             (iv_addr_mac_p2             ),
.iv_rdata_mac_p2                            (iv_rdata_mac_p2            ),
                                            
.i_wr_mac_p3                                (i_wr_mac_p3                ),
.iv_addr_mac_p3                             (iv_addr_mac_p3             ),
.iv_rdata_mac_p3                            (iv_rdata_mac_p3            ),

.i_wr_tau                                   (i_wr_tau    ), 
.iv_addr_tau                                (iv_addr_tau ), 
.iv_rdata_tau                               (iv_rdata_tau) 
); 

global_registers_management global_registers_management_inst(
.i_clk                            (i_clk                                 ),                
.i_rst_n                          (i_rst_n                               ),      
                                                                         
.iv_addr                          (ov_addr                       ),              
.iv_wdata                         (ov_wdata                      ),         
.i_wr                             (w_wr_cpa2grm                          ),      
.i_rd                             (w_rd_cpa2grm                          ),      
                                                                         
.o_wr                             (w_wr_grm2cag                          ),        
.ov_addr                          (wv_addr_grm2cag                       ),      
.ov_rdata                         (wv_rdata_grm2cag                      ),      

.ov_tse_ver                       (ov_tse_ver                            ),
.ov_hpriority_be_police_threshold (ov_hpriority_be_police_threshold), 
.ov_rc_threshold_value            (ov_rc_threshold_value           ),
.ov_lpriority_be_police_threshold (ov_lpriority_be_police_threshold),
.o_qbv_or_qch                     (o_qbv_or_qch                    ),          
.ov_time_slot_length              (ov_time_slot_length             ),          
.ov_schedule_period               (ov_schedule_period              )  
);   
endmodule